Assignment Task
1. Purpose
In this lab, you will design and build a simple code converter circuit using the Nexys 4 DDR Development board, which is designed around the Xilinx Artix-7. During this laboratory, you will gain experience using the Xilinx Vivado digital circuit development tools.
2. Background
Converting data from a human-friendly format into a form that is understandable by a machine is a key concept in any digital logic design environment. Computers and digital logic circuits in general, are only able to interpret data in binary form. Every form of data, from integers to characters, must be converted into a binary string in order for a computer to be able to manipulate and store them. This process is called encoding the data for use in a computer. Literally any data-encoding scheme will work as long as data is converted into a binary form that the computer is programmed to understand. For this reason, there are numerous different binary codes that may all represent the same thing. For instance, the ASCII code (American Standard Code for Information Interchange) utilizes a seven-bit string to represent 128 basic text characters, numbers, and control characters used in word processing. More recently, with the introduction of the Internet and globalization, a new code has been required to handle a vastly greater number of characters from languages throughout the world. Unicode was introduced to handle the vast number of characters and symbols now required for worldwide communication. It uses up to 24-bits and several encoding algorithms to achieve this. Clearly, a machine using ASCII codes would need some form of data conversion processing to understand Unicode, and vice-versa. In fact, many web pages containing foreign languages may not be displayed correctly depending on the Unicode support a given web browser allows. This laboratory experiment will be focused on data conversion, but nothing as complicated as ASCII to Unicode. When all that is required is to encode integers from 0 through 9, encoding data becomes much simpler, although there are still a great number of different encodings that are possible. Binary Coded Decimal (BCD) is a code that uses four bits to represent each of the digits from 0 to 9. Each integer value is encoded directly in its binary form, producing several unused four-bit combinations. Excess-3 code is similar to BCD in that it uses a four-bit encoding for each integer value, however, when an integer is encoded, its value is first incremented by three, then converted to its binary form. The overall effect is to add three to all the Natural BCD codes. While Natural BCD encoding has six unused codes at the high end of the binary conversion (10 and above), Excess-3 BCD has three unused codes at the low end (2 and below) and three at the high end (13 and above). Table 1 shows the integer values from 0 through 9 and their corresponding Natural BCD and Excess-3 BCD encodings.
3. Preliminary Design
In this laboratory, two different code conversion circuits will be designed based upon the data encodings in Table 1. The first circuit will capture an input number from the user in Natural BCD form, and will output its Excess-3 BCD representation. The second circuit that will be built will perform both code conversion processes depending on the state of a selection input, SEL. When the selection input is low, the conversion will take in Natural BCD and output Excess-3 BCD, just like the first conversion circuit described above. However, when the selection input is high, this new circuit reads a number in Excess-3 BCD and outputs its Natural BCD counterpart. Figure 1 below contains block diagrams for both of these circuits.
With the exception of not including the unused codes for Natural BCD, Table 1 above is essentially the truth table for the first circuit to be designed for this laboratory. Using this truth table, the logic functions for each output of the simple code converter can be relatively easily obtained and minimized using Karnaugh Maps. Recognize that the outputs for the Universal Code Converter depend on one more input, namely the select input, which makes Karnaugh Map minimization slightly more difficult than with the Simple Code Converter. Design of this circuit can be made easier, however, by recognizing that the select input simply chooses between two independent sets of functionality.
1. Develop the logic functions for each output of the Simple Code Converter. Create the full truth table, and minimize the logic using Karnaugh Maps or another preferred method of your choice. Be sure to capitalize upon DON’T CARE conditions where possible.
2. Create the full truth table for the Universal Code Converter circuit. Be sure to include DON’T CARE terms where they apply.
3. From this truth table, derive the logic functions for each output of the Universal Code Converter. Note that the truth table is identical to that for the Simple Code Converter when the select input is zero. You may, therefore, minimize only the half of the truth table corresponding to a select input value of one. The select input may then be used as a conditional check within an IF statement when the circuit is implemented.
4. Bring the output logic functions for each of the two circuits to the laboratory where they will be implemented using VHDL code. The laboratory procedure will then discuss the steps for creating the necessary VHDL code, simulating both designs, and programming Nexys 4 DDR development board.
In the Lab
The in-lab portion of this laboratory procedure is divided into two main parts: the Simple Code Converter and the Universal Code Converter. The procedure for the Simple Code Converter contains an in-depth walkthrough of project creation, simulation, and programming of the Nexys 4 DDR development board, in addition to the basic operations offered by the VHDL language that will be necessary to specify the functionality of the code converter itself. The procedure for the Universal Code converter will then introduce some additional operations offered by the VHDL language that facilitate a simplified specification of the expanded code conversion functionality.
The Simple Code Converter
1. Begin by starting the Vivado Project Navigator software. If there is already a project running, close that project and create a New Project. This is done under the File drop-down menu, just like creating a new file in most other applications.
2. In the dialog box that pops up, set the directory in which you would like all the files you will create to be saved, and enter the name of the project you would like to create. All the files created by the Vivado tools will be placed in a file with the project name specified by you, which itself resides in the directory you picked.
3. Select RTL Project from the next window and hit Next >.. Confirm the Target Language is VHDL and simulator Language is Mixed. Under Add Sources hit the center green button. From the dialog box select Create File. Select VHDL as the file type and select an appropriate file name then hit Next three times.
4. In the next dialog box, under parts, select xc7a100tcsg324-1, hit Next >. On the next window, hit Finish to conclude creating your project.
5. When the set up is finished a Define Module dialog window will appear. In this all of the ports for the VHDL module will be created. Under port name input appropriate names for all the ports in the module. Under Direction select if it is an input or output. Once all ports are created hit
The Universal Code Converter
1. Much of the basic work for the Universal Code Converter is the same as for the Simple Converter; so, if there are any questions about how to proceed beyond the instruction given here, see the previous section of this laboratory procedure.
2. Open a new project and add a VHDL module to it. The main difference between this circuit and the Simple Converter is the addition of the select signal to change the functionality. While the output functions could be found using five variable Karnaugh Maps, the selectable nature of this circuit lends itself nicely to the use of IF statements.
3. In order to use IF statements, they must be nested within a PROCESS declaration. To make your code into a process, between the “begin” and “end” statements of the architecture code (where your functionality was entered for the Simple Converter); enter PROCESS followed by all the input signals in parentheses on the same line. On the next line, enter BEGIN, then leave a few lines of space and finally enter “END PROCESS;” to complete the process. The result should appear as follows: Laboratory Experiment 1-8 PROCESS (input_signal1, input.
